11 research outputs found
Symbol-Based Successive Cancellation List Decoder for Polar Codes
Polar codes is promising because they can provably achieve the channel
capacity while having an explicit construction method. Lots of work have been
done for the bit-based decoding algorithm for polar codes. In this paper,
generalized symbol-based successive cancellation (SC) and SC list decoding
algorithms are discussed. A symbol-based recursive channel combination
relationship is proposed to calculate the symbol-based channel transition
probability. This proposed method needs less additions than the
maximum-likelihood decoder used by the existing symbol-based polar decoding
algorithm. In addition, a two-stage list pruning network is proposed to
simplify the list pruning network for the symbol-based SC list decoding
algorithm.Comment: Accepted by 2014 IEEE Workshop on Signal Processing Systems (SiPS
A Reduced Latency List Decoding Algorithm for Polar Codes
Long polar codes can achieve the capacity of arbitrary binary-input discrete
memoryless channels under a low complexity successive cancelation (SC) decoding
algorithm. But for polar codes with short and moderate code length, the
decoding performance of the SC decoding algorithm is inferior. The cyclic
redundancy check (CRC) aided successive cancelation list (SCL) decoding
algorithm has better error performance than the SC decoding algorithm for short
or moderate polar codes. However, the CRC aided SCL (CA-SCL) decoding algorithm
still suffer from long decoding latency. In this paper, a reduced latency list
decoding (RLLD) algorithm for polar codes is proposed. For the proposed RLLD
algorithm, all rate-0 nodes and part of rate-1 nodes are decoded instantly
without traversing the corresponding subtree. A list maximum-likelihood
decoding (LMLD) algorithm is proposed to decode the maximum likelihood (ML)
nodes and the remaining rate-1 nodes. Moreover, a simplified LMLD (SLMLD)
algorithm is also proposed to reduce the computational complexity of the LMLD
algorithm. Suppose a partial parallel list decoder architecture with list size
is used, for an (8192, 4096) polar code, the proposed RLLD algorithm can
reduce the number of decoding clock cycles and decoding latency by 6.97 and
6.77 times, respectively.Comment: 7 pages, accepted by 2014 IEEE International Workshop on Signal
Processing Systems (SiPS
Efficient decoder design for error correcting codes
Error correctiong codes (ECC) are widly used in applications to correct errors in data transmission over unreliable or noisy communication channels. Recently, two kinds of promising codes attracted lots of research interest because they provide excellent error correction performance. One is non-binary LDPC codes, and the other is polar codes. This dissertation focuses on efficient decoding algorithms and decoder design for thesetwo types of codes.Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for non-binary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and hence have significantly lower complexity than other algorithms. We propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the ex-isting majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a re-selection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, re-selectingintermediate hard decisions, and changing reliability information.Polar codes are of great interests because they provably achieve the symmetric capacity of discrete memoryless channels with arbitrary input alphabet sizes an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. We propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. Then wepropose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination has lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arıkan’s channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. To reduce the complexity of the list pruning, atwo-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Since memory is a significant part of SCL decoders, we also propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder.To reduce the complexity of the recursive channel combination further, we propose an approximate ML (AML) decoding unit for SCL decoders. In particular, we investigate the distribution of frozen bits of polar codes designed for both the binary erasure and additive white Gaussian noise channels, and take advantage of the distribution to reduce the complexity of the AML decoding unit, improving the throughput-area efficiency of SCL decoders.Furthermore, to adapt to variable throughput or latency requirements which exist widely in current communication applications, a multi-mode SCL decoder with variable list sizes and parallelism is proposed. If high throughput or small latency is required, the decoder decodes multiple received words in parallel with a small list size. However, if error performance is of higher priority, the multi-mode decoder switches to a serialmode with a bigger list size. Therefore, the multi-mode SCL decoder provides a flexible tradeoff between latency, throughput and error performance at the expense of small overhead
Etude de la suppression du bruit acoustique dans les systemes de reconnaissance vocale
SIGLECNRS TD Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc